1. Field of the Invention
This invention relates generally to the cell structure and fabrication method of the memory cell and arrays. More particularly, this invention relates to a novel and improved cell structure and fabrication process including a novel silicide segment as polysilicon via replacement thus functions as diffusion barrier to prevent reduction of the load resistance from diffusion of the heavily doped regions whereby a polysilicon load punch through can be prevented even with reduced length of the polysilicon load resistor.
2. Description of the Prior Art
A major difficulty faced by those who are attempting to reduce the size of a memory cells is a length requirement of a polycrystalline silicon layer employed as a load resistor for the memory cell. For example, the load resistors used in a memory cells as pull-up resistors must have high value of resistance to prevent a punch-through. As these resistors are formed as part of the polycrystalline layer wherein portions of the layer are employed as connector which are therefore doped with higher dopant concentration to provide lower connector resistance. Extra length of polysilicon layer becomes a design requirement due to the concern of lateral diffusion from these heavily doped regions during the thermal cycles thus causing a reduction of resistance. The length requirement thus hinders the size of the cell to be further miniaturized. Due to the concern of resistance reduction resulting from lateral diffusion, the potential problem of polysilicon load punch through also becomes a design limitation particularly with memory array of smaller cell size.
In order to better understand the background of the invention, a conventional method for implementing a load resistor on a polycrystalline layer is first described according to FIGS. 1A to 1C. In FIG. 1A, a cross sectional view is illustrated wherein a sequence of standard memory cell manufacture processes are performed on a substrate to carry out the processing steps of isolation, well formation and V.sub.th dose implantation for adjusting the threshold voltage. A gate oxide layer is grown followed by depositing the first polycrystalline silicon layer and optionally a silicide deposition as shown in FIG. 1A. Referring to FIG. 1B, the gate region is patterned followed by a LDD and a source/drain (S/D) formation process. A TEOS oxide layer is then deposed on the top surface and the polysilicon via is formed.
Referring to FIG. 1C, a second polysilicon layer is formed followed by a blank implant with a low dose implanting ions to adjust the load resistance of the second polysilicon layer. The second polysilicon layer is then patterned wherein part of the second polysilicon layer, i.e., polysilicon (2), will be utilized as a connector and the remaining portion of that layer is applied as a load resistor. The portion utilized as a connector is more heavily doped. The sequence of implant the connector and the patterning of the second polysilicon layer can be exchanged. The processing steps and the resulting configuration generate a particular problem for the load resistor, i.e., the N.sup.- segment disposed between two more heavily doped N.sup.+ segments. Namely, a lateral diffusion of the implanted ions in the more heavily N.sup.+ segment will cause the implanted ions to diffuse into the load resistor segment which is more lightly doped N.sup.- segment. The resistance of the load resistor will be adversely reduced and a potential problem of punch through may be resulted from the load resistance reduction. In order to assure sufficient resistance is maintained after the thermal cycles, extra length of the polysilicon layer (2) is provided in anticipation of the reduction of the effective length caused by lateral diffusion during high temperature cycles in subsequent processing steps. Therefore, size reduction of a memory cell is limited by the length of the second polysilicon layer which is employed as load resistor. A minimum length is required for this second polysilicon layer in order to prevent the occurrence of a punch through which may be induced during the thermal cycles in the manufacturing process leading to the lateral diffusion and resistance reduction of the load resistor.
In U.S. Pat. No. 5,172,211, entitled "High Resistance Polysilicon Load Resistor" (issued on Dec. 15, 1992), Godinho et al. disclose a load resistor used in a semiconductor integrated circuit which consists of two portions of conductive material, typically strips of either a silicide or a composite polycrystalline silicon layer and silicide layer formed thereon. The strips are formed on a semiconductor substrate and separated from each other by a selected distance. An electrically conductive dopant diffusion barrier is formed on the first and second portions of conductive material. A polycrystalline silicon layer is then placed on the structure such that one portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the first portion of conductive material and the other portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the second portion of the conductive material. The diffusion barrier layer serves to prevent any dopant from the conductive material from diffusing into the polycrystalline silicon, i.e., polysilicon, material thereby allowing the polycrystalline silicon material to function as a load resistor having a high resistance.
The load resistor disclosed by Gadinho et al. provides a solution to maintain the resistance of the load resistor by forming dual separated polysilicon strips and implementing a diffusion barrier between these strips thus creating a high resistance load resistor which being affected by lateral diffusion of dopant into the resistor. However, Gadinho's device requires more complicate processing steps in forming two separate polysilicon strips and then a diffusion barrier between them. The production costs for implementing the structural features is increased due to the more complicate manufacturing processes. Product yield and reliability of the memory device may also be adversely affected when more complicate processing steps are performed.
Therefore, a need still exists in the art of memory cell design and manufacture to provide a novel cell structure and manufacture process to resolve the above difficulties. It is desirable that the novel memory cell architecture can significantly relieve the limitation that a smaller memory cell often encounter a punch through problem at the polysilicon load. By resolving this particular limitation would allow the cell size to be further reduced. Additionally, it is desirable that this novel cell structure and manufacture process would be simple and convenient to carry out such that the quality of the transistor array and production cost would not be adversely affected by a more complicate manufacture process.